XDMA

XDMA block use "DMA for PCI Express (PCIe) Subsystem" IP supported by AMD. You can click the IP in block design to see the configuration parameters. For Kiwi device:

  • Use 4 lanes at full speed 8GT/s
  • Axilite 32 bits
  • Axilite master space 32MB
  • Axistream 128 bits, clock 250MHz
  • Use full 4 axistream channels (H2C/C2H)

The picture below shows the actual number of channel and purpose of each channel

XDMA channels

From Axil of XDMA, connect with AXI Interconnect IP to divide address space for sub-modules. Changing the size of address space depends on the number of registers need to be written through Axil to Axil of sub-modules. You can check the Axil address distribution in block design or in the table below:

OffsetRangeTarget RTL module/ IP
0x0000_00000x0000_1000 4Ktdc/tdc_mngt/TDC_REG_MNGT_v1_0.v
0x0000_10000x0000_1000 4Kddr4/ddr_data_reg_mngt.v
0x0001_00000x0000_1000 4Kfastdac/jesd204b_tx_wrapper.v
0x0001_20000x0000_1000 4Kclk_rst/clk_rst_mngt.v
0x0001_30000x0000_1000 4Ktdc/time_spi/axi_quad_spi
0x0001_50000x0000_1000 4Kttl_gate_apd.v
0x0001_60000x0000_1000 4Kdecoy.v
0x0002_00000x0001_0000 8Kspi_dacs_ltc/axi_quad_spi
0x0003_00000x0008_0000 64Kfastdac/jesd_transport.v