TDC

We use AS6501 TDC(Time to Digital Converter) chip to convert arriving time of q-bit to digital data. All modules and IP manage in/out signals from TDC are grouped under block tdc:

overview

clk_rst_buffer

tdc_olvds.v: buffer for differential output signals, clocks

Signals nameInterfaceDirInit statusDescription
tdc_lclkiClockI-source lclk for TDC chip
tdc_refclkClockI-source refclk for TDC chip
tdc_rstidxResetI-source rstidx for TDC chip
tdc_lclki_n/ptdc_ext_clkrstO-lclk differential pair output
tdc_refclk_n/ptdc_ext_clkrstO-refclk differential pair output
tdc_rstidx_n/ptdc_ext_clkrstO-rsridx differential pair output

tdc_ilvds.v: buffer for differential input signals,clocks

Signals nameInterfaceDirInit statusDescription
lclk_n/ptdc_ext_inI-lclk pair received from TDC chip
frameA_n/ptdc_ext_inI-frameA pair received from TDC chip
frameB_n/ptdc_ext_inI-frameB pair received from TDC chip
sdiA_n/ptdc_ext_inI-sdiA pair received from TDC chip
sdiB_n/ptdc_ext_inI-sdiB pair received from TDC chip
O_lclk-O-lclk in single-ended
O_frameA-O-frameA in single-ended
O_frameB-O-frameB in single-ended
O_sdiA-O-sdiA in single-ended
O_sdiB-O-sdiB in single-ended

tdc_clk_rst_mngt.v : generate refclk 5MHz, rstindex for TDC; generate simulated STOPA signal for TDC

Signals nameInterfaceDirInit statusDescription
clk200_iClockI-clock source 200MHz
tdc_rstResetI-reset active HIGH
pps_i-I-pps input from WRS
stopa_sim_limit[31:0]-I-registers to set division limit for stopa_sim
stopa_sim_enable_i-I-pull to high to update registers
tdc_refclk_o-O-generated refclk for TDC
tdc_rstidx_o-O-generated reset index for TDC
pps_trigger-O-trigger PPS event
stopa_sim-O-simulated STOPA of TDC
  • User parameters of tdc_clk_rst_mngt
User Parameter nameValueDescription
N_COUNTER_APD800STOPA rate = 200M/(N_COUNTER_APD*divide_stopa)
N_TDC_REFCLK8Every 8 periods of refclk, generate a rstidx
TDC_DIV_HALF20refclk (MHz) = 200 (MHz) / (TDC_DIV_HALF*2)

time_spi

Quad AXI spi: IP of AMD, manage to transfer data from AXI bus to spi bus. All information of IP is provided by Xilinx

spi_inout_mngt.v: mananage inout pins from quad AXI spi to physical spi pins

Signals nameInterfaceDirInit statusDescription
mosi_iocom_ext_spiIO-SPI MOSI
miso_iocom_ext_spiIO-SPI MISO
ss_io[1:0]com_ext_spiO-SPI SS (2 bits for TDC and JITCLEAN)
sck_iocom_ext_spiO-SPI SCLK
in0_i-I-connect io0_o of Quad AXI spi
in0t_i-I-connect io0_t of Quad AXI spi
out0_o-O-connect io0_i of Quad AXI spi
in1_i-I-connect io1_o of Quad AXI spi
in1t_i-I-connect io1_t of Quad AXI spi
out1_o-O-connect io1_i of Quad AXI spi
sck_i-I-connect sck_o of Quad AXI spi
sckt_i-I-connect sck_t of Quad AXI spi
sck_o-O-connect sck_i of Quad AXI spi
ss_i[1:0]-I-connect ss_o of Quad AXI spi
sst_i-I-connect ss_t of Quad AXI spi
ss_o[1:0]-O-connect ss_i of Quad AXI spi
rst_jic-OHIGHreset jitter cleaner

system_ila_tdc

ILA debug core, probes signals under tdc blocks

tdc_mngt

tdc_core.v:

Manages digital data from TDC, output tdc time/global counter/click result depends on axil commands.

Signals nameInterfaceDirInit statusDescription
m_axis signalsm_axisIO-match with s_axis interface of fifo_gc_tdc_rtl.v
sr signalssrIO-match with mr interface
lclk_iClockI200MHzlclk
clk200_iClockI200MHzclk200
m_axis_clkClockI200MHzclock for m_axsi interface
lrst_iResetIActive HIGHreset in domain lclk
gc_rstResetIActive HIGHreset in domain clk200
fifo_calib_rstResetOActive LOWreset for the s_axis interface of fifo_gc
linterrupt_i-I-interrupt signal from TDC
frame_i-I-frame signal from TDC
sdi_i-I-sdi signal from TDC
pps_i-I-PPS signal from WRS
rd_en_4-I-enable signal at 40MHz
tvalid200-O-indicates gc is valid in clk200 domain
tdata200-O-time data value in clk200 domain
gc_time_valid[47:0]-O-gc value at the moment time data is valid
q_gc_time_valid_mod16[3:0]-O-gc value modulo 16 in 80MHz
tdata200_mod[15:0]-O-tdata200%625
gate_pos0[31:0]-O-pos0 of soft_gate0
gate_pos1[31:0]-O-pos1 of soft_gate0
gate_pos2[31:0]-O-pos0 of soft_gate1
gate_pos3[31:0]-O-pos1 of soft_gate1
others-O-other signals is for debug

tdc_reg_mngt.v:

Manages axilite registers.

User parameters: |Parameter |Value |Description |--------------------|------|------------ |C_S_Axil_Addr_Width |12 |Address width of axil interface |C_S_Axil_Data_Width |32 |Address width of axil interface

Port descriptions

Signals nameInterfaceDirInit statusDescription
standard axil signalss_axilIO-s_axil interface for w/r registers
mr signalsmrIO-registers of modules AS6501_IF.v (details in Axil registers)
stopa_sim_limit[31:0]-O-registers tdc_clk_rst_mngt.v (details in Axil registers)
stopa_sim_enable_o-O-registers tdc_clk_rst_mngt.v (details in Axil registers)
s_axil_aclkClockI15MHzclock for axil interface
s_axil_aresetnResetIActive LOWreset for axil interface

fifo_gc_tdc_rtl.v:

Instantiates fifo_gc_tdc, this fifo is axistream fifo. Instantiate axistream fifo in an RTL module allows to modify FREQ_HZ parameter of axistream interface when rebuild the block design.

Signals nameInterfaceDirInit statusDescription
s_axis_tdata [127:0]s_axisI-axis stream data gc in
s_axis_tuser [3:0]s_axisI-axis stream tuser
s_axis_tvalids_axisI-axis stream valid
s_axis_treadys_axisO-axis stream ready
m_axis_tdata [127:0]m_axisO-axis stream data gc out
m_axis_tuser [3:0]m_axisO-axis stream tuser
m_axis_tvalidm_axisO-axis stream valid
m_axis_treadym_axisI-axis stream ready
m_aclkClockI250MHzclock for m_axis interface
s_aclkClockI200MHzclock for s_axis interface
s_aresetnResetI-reset for s_axis interface, active low

Axil registers

  • Base address: 0x0000_0000
  • Offset address slv_reg(n) : 4*n

slv_reg0 - R/W Access - Trigger Control

BitsSignal nameHW WireAction/ValueDescription
31:1---Reserved 0
0tdc_enablemr_enablepull LOW to HIGHEnable signal to receive sdi and frame from TDC

slv_reg1 - R/W Access - Configuration

BitsSignal nameHW WireAction/ValueDescription
31:16---Reserved 0
15:14tdc_index_stop
_bitwise_o
mr_index_stop
_bitwise_i
-Reserved 0
13:8tdc_index_stop
_bitwise_o
mr_index_stop
_bitwise_i
default:14Define stop bitwise (match with TDC)
7:6tdc_index_stop
_bitwise_o
mr_index_stop
_bitwise_i
-Reserved 0
5:0tdc_index_stop
_bitwise_o
mr_index_stop
_bitwise_i
default:4Define index bitwise (match with TDC)

slv_reg2 - R/W Access - Trigger Control

BitsSignal nameHW WireAction/ValueDescription
31:1---Reserved 0
0start_gc_omr_start_gc_ipull LOW to HIGHEnter START state of tdc

slv_reg3 - R/W Access - Configuration

BitsSignal nameHW WireAction/ValueDescription
31:16stopa_sim_limitstopa_sim_limitmax 512limit high: end of duty cycle
15:8stopa_sim_limitstopa_sim_limitmax 256limit_low : begin of duty cycle
7:0stopa_sim_limitstopa_sim_limitmax 256divide_stopa

It depends on frequency of STOPA(in tdc_clk_rst_mngt.v) to set limit high and limit low for duty cycle. The limit value is in unit of clk200 period

slv_reg4 - R/W Access - Configuration

BitsSignal nameHW WireAction/ValueDescription
31:24gate0_omr_gate0_imax 256define soft gate0 width
23:0gate0_omr_gate0_imax 625define soft gate0 start postion
  • Qubit rate is 80MHz(12.5ns)
  • TDC resolution is 20ps
  • Gate position should be in range 0..625

slv_reg5 - R/W Access - Configuration

BitsSignal nameHW WireAction/ValueDescription
31:24gate1_omr_gate1_imax 256define soft gate1 width
23:0gate1_omr_gate1_imax 625define soft gate1 start postion

slv_reg6 - R/W Access - Configuration

BitsSignal nameHW WireAction/ValueDescription
31:16---Reserved 0
15:0shift_tdc_time_omr_shift_tdc_time_i-Define small shift for tdc time

slv_reg7 - R/W Access - Configuration

BitsSignal nameHW WireAction/ValueDescription
31:16---Reserved 0
15:0shift_gc_back_omr_shift_gc_back_i-Define small offset for gc

slv_reg8 - R/W Access - Configuration

BitsSignal nameHW WireAction/ValueDescription
31:3---Reserved 0
2:0tdc_command_omr_command_i-Define with mode (continuous or gated) to output gc

slv_reg9 - R/W Access - Trigger Control

BitsSignal nameHW WireAction/ValueDescription
31:3---Reserved 0
2stopa_sim_enable_ostopa_sim_enablePull LOW to HIGHEnable register update for stopa_sim
1tdc_reg_enable200_omr_reg_enable200_iPull LOW to HIGHUpdate registers in clk200 domain
0tdc_reg_enable_omr_reg_enable_tdc_iPull LOW to HIGHUpdate registers in lclk domain

slv_reg10 - R/W Access - Trigger Control

BitsSignal nameHW WireAction/ValueDescription
31:1---Reserved 0
0tdc_command_enable_omr_command_enablepull LOW to HIGHStart filling gc to fifo

slv_reg14 - R Access - Monitoring

BitsSignal nameHW WireAction/ValueDescription
31:0click1_count_imr_click1_count_o-monitoring click in soft_gate1

slv_reg15 - R Access - Monitoring

BitsSignal nameHW WireAction/ValueDescription
31:0click0_count_imr_click0_count_o-monitoring click in soft_gate0

slv_reg16 - R Access - Monitoring

BitsSignal nameHW WireAction/ValueDescription
31:0total_count_imr_total_count_o-monitoring total click in gated APD

Data flow

Picture below shows an overview how data flows through modules and xdma channels. Responses to commands are written in modules tdc_core.v

tdc data flow

Software control functions

Setting registers used in state machine under clk200

def Time_Calib_Reg(command,t0, gc_back, gate0, width0, gate1, width1):
    BaseAddr = 0x00000000
    Write(BaseAddr + 16,hex(int(width0<<24 | gate0))) #gate0
    Write(BaseAddr + 20,hex(int(width1<<24 | gate1))) #gate1
    Write(BaseAddr + 24,hex(int(t0))) #shift tdc time = 0
    Write(BaseAddr + 28,hex(int(gc_back))) #shift gc back = 0
    Write(BaseAddr + 32,hex(int(command))) #command = 1: raw | =2: with gate
    Write(BaseAddr + 36,0x0)
    Write(BaseAddr + 36,0x2)# turn bit[1] to high to enable register setting

Initialize tdc module, global counter in tdc module is local, it means it's available in Bob only for calibration purpose. There are 2 state machines in tdc module:

  • state machine under lclk_i: Config_Tdc() sets registers and enable this state machine, output digital data in FPGA
  • state machine under clk200: Reset_gc() and Start_gc() send command to reset and start global counter
def Time_Calib_Init():
    Config_Tdc() #Get digital data from TDC chip
    Reset_gc() #Reset global counter
    Start_gc() #Global counter start counting at the next PPS

Get detection result, function Get_Stream() includes reset fifo_gc_tdc and read data from xdma0_c2h_*.

def Cont_Det(): 
    num_data = 2000
    Get_Stream(0x00000000+40,'/dev/xdma0_c2h_2','data/tdc/output_dp.bin',num_data)
    command ="test_tdc/tdc_bin2txt data/tdc/output_dp.bin data/tdc/histogram_dp.txt"
    s = subprocess.check_call(command, shell = True)

    time_gc = np.loadtxt("data/tdc/histogram_dp.txt",usecols=(1,2),unpack=True)
    int_time_gc = time_gc.astype(np.int64)
    duration = (max(int_time_gc[1])-min(int_time_gc[1]))*25
    click_rate = np.around(num_data/(duration*0.000000001),decimals=4)
    print("Number of count: ", str(len(int_time_gc[1])))
    print("Appro click rate: ", str(click_rate), "click/s")